1 features features features features features detects 12khz and 16khz spm detects 12khz and 16khz spm detects 12khz and 16khz spm detects 12khz and 16khz spm detects 12khz and 16khz spm frequencies frequencies frequencies frequencies frequencies lo lo lo lo lo w p w p w p w p w p o o o o o wer (3.0 wer (3.0 wer (3.0 wer (3.0 wer (3.0 v v v v v olt olt olt olt olt min min min min min <1.0ma) <1.0ma) <1.0ma) <1.0ma) <1.0ma) operation operation operation operation operation high speec high speec high speec high speec high speec hband rejection hband rejection hband rejection hband rejection hband rejection pr pr pr pr pr oper oper oper oper oper ties ties ties ties ties product information product information product information product information product information fig.1 functional block diagram FX631 FX631 FX631 FX631 FX631 lo lo lo lo lo w-v w-v w-v w-v w-v olta olta olta olta olta g g g g g e spm detector e spm detector e spm detector e spm detector e spm detector t t t t t one-follo one-follo one-follo one-follo one-follo wer and p wer and p wer and p wer and p wer and p ac ac ac ac ac ket mode ket mode ket mode ket mode ket mode outputs outputs outputs outputs outputs applications applications applications applications applications comple comple comple comple comple x and/or simple x and/or simple x and/or simple x and/or simple x and/or simple t t t t t elephone systems elephone systems elephone systems elephone systems elephone systems call-char call-char call-char call-char call-char g g g g g e/-log e/-log e/-log e/-log e/-log ging ging ging ging ging systems systems systems systems systems + - 1 32 period measure tone follower logic packet tone logic divider signal in (-) amp out xtal/clock (12khz/16khz) system system system clock in clock out tone follower output v ss v dd v bias packet mode output signal in (+) level detector +20db 12khz/16khz xtal clock dividers input amp xtal/clock oscillator brief description brief description brief description brief description brief description the FX631 is a low-power, system-selectable subscriber pulse metering (spm) detector to indicate the presence, on a telephone line, of both 12khz and 16khz telephone call-charge frequencies. deriving its input directly from the telephone line, input amplitude/sensitivities are component adjustable to the user's national must/must-not decode specifications via an on-chip input amplifier, whilst the 12khz and 16khz frequency limits are accurately defined by the use of an external 3.579545mhz telephone-system xtal or clock-pulse input. the FX631, which demonstrates high 12khz and 16khz performance in the presence of both voice and noise, can operate from either a single or differential analogue signal input from which it will produce two individual logic outputs. 1. tone follower output - a 'tone-following' logic output producing a low level for the period of a correct decode and a high level for a bad decode or n otone . 2. packet (cumulative tone) mode output - to respond and de-respond after a cumulative 40ms of good tone (or n otone ) in any 48ms period. this process will ignore small fluctuations or fades of a valid frequency input and is available for processor wake-up, minimum tone detection, n otone indication or transient avoidance. this system (12khz/16khz) selectable microcircuit, which may be line-powered, is available in 16-pin plastic dil and surface mount soic and 24-pin plastic ssop packages. cml semiconductor products cml semiconductor products cml semiconductor products cml semiconductor products cml semiconductor products FX631 FX631 FX631 FX631 FX631 publication d/631/8 july 1998
2 2.3 pin function description xtal the input of the oscillator inverter. xtaln the output of the oscillator inverter clkin the input to the internal clock divider circuitry. when a 3.579545mhz crystal is used, it should be connected across xtal & xtal and xtal should be directly connected to clkin. no other external components are necessary because the other oscillator components (capacitor, resistor) are on chip. when an externally available clock signal is used, it should be inserted at clkin. xtal should be tied to vdd or vss and xtal should be left open circuit. system a logic input pin which controls whether the device detects 12khz spm tones (logic 1) or 16khz spm tones (logic 0). it has an internal 1 mohm pull- up resistor (l 2khz). negip the negative input, positive input and output respectively of the gain adjusting posip amplifier. ampop external components are used in conjunction with the op -amp according to the required level sensitivity and depending on whether the incoming signal is differential or common mode. vdd the power supply, ground and filter bias pins respectively. vss bias voo and bias should each be de- coupled, via a 1 .0@f capacitor, to vss. ttfop true tone follower output. this is the pin that responds and de- responds within 4ms of a good tone appearing or disappearing. it is thus like an envelope of the spm tone. logic 0 represents detect and logic 1 represents not detect. dtfop this is the output of the delayed tone follower block. it will respond when 40ms of good tone has been received within any 48ms window. the 48ms is divided into 24 packets of 2ms each (16khz mode) or 15 packets of 2.667ms each (12khz mode). each packet represents 32 cycles of spm frequency. the window is a shifting window, ie. the 48ms window is assessed every 2ms (16khz mode) or 2.667ms (12khz). if the necessary number of good packets are consecutive, the output will respond in the minimum time of 40ms. logic 0 represents detect and logic 1 represents not detect. xtal/clock: xtal/clock: xtal/clock: xtal/clock: xtal/clock: the input to the on-chip clock oscillator; for use with a 3.579545mhz xtal in conjunction with the xtal output (see figure 2); circuit components are on chip. using this mode of clock operation, the clock out pin should be connected directly to the clock in pin. if a clock pulse input is employed to the clock in pin, this pin must be connected directly to v dd (see figure 2). xtal: xtal: xtal: xtal: xtal: the output of the on-chip clock oscillator inverter. clock out: clock out: clock out: clock out: clock out: a clock signal derived from the on-chip xtal oscillator. if the on-chip oscillator is used, this pin should be connnected directly to the clock in pin. this output should not be used to clock other devices. clock in: clock in: clock in: clock in: clock in: the 3.579545mhz clock pulse input to the internal clock-dividers. if a clock pulse input is employed, the xtal/clock input (pin 1) should be connected to v dd . see figure 2. v v v v v bias bias bias bias bias : : : : : the output of the on-chip analogue bias circuitry. held internally at v dd /2, this pin should be decoupled to v ss (see figure 2). v v v v v ss ss ss ss ss : : : : : negative supply rail (gnd). signal in (+): signal in (+): signal in (+): signal in (+): signal in (+): signal in (-): signal in (-): signal in (-): signal in (-): signal in (-): amp out: amp out: amp out: amp out: amp out: tone follower output: tone follower output: tone follower output: tone follower output: tone follower output: this output provides a logic 0 (low) for the period of a detected tone, and a logic 1 (high) for n otone detection. see figure 7. packet mode output: packet mode output: packet mode output: packet mode output: packet mode output: a logic output that will be available after a cumulation of 40ms of 'good' tone has been received. this packet mode tone follower will only respond when a tone frequency of sufficient quality has been received for sufficient time, i.e. a cumulation of 40ms in any 48ms, short tone bursts or breaks will be ignored. this output provides a logic 0 (low) for a detected tone and a logic 1 (high) for n otone detection. see figure 7. system: system: system: system: system: the logic input to select device operation to either 12khz (logic 1 - high) or 16khz (logic 0 - low) spm systems. this input has an internal 1m w pullup resistor (12khz). v v v v v dd dd dd dd dd : : : : : positive supply rail. a single, stable power supply is required. critical levels and voltages within the FX631 are dependant upon this supply. this pin should be decoupled to v ss by a capacitor mounted close to the pin. note that if this device is line powered, the resulting supply must be stable. see notes on microcircuit protection from high and spurious line voltages. no internal connection, leave open circuit. FX631 FX631 FX631 FX631 FX631 d5 d5 d5 d5 d5 1 1 1 1 1 4 4 4 4 4 5 5 5 5 5 6 6 6 6 6 8 8 8 8 8 12 12 12 12 12 13 13 13 13 13 17 17 17 17 17 18 18 18 18 18 19 19 19 19 19 20 20 20 20 20 21 21 21 21 21 24 24 24 24 24 2, 3, 7, 9, 10, 11, 14, 15, 16, 22, 23 pin number pin number pin number pin number pin number function function function function function FX631 FX631 FX631 FX631 FX631 dw/p dw/p dw/p dw/p dw/p 1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 4 4 7 7 7 7 7 8 8 8 8 8 9 9 9 9 9 10 10 10 10 10 11 11 11 11 11 13 13 13 13 13 14 14 14 14 14 15 15 15 15 15 16 16 16 16 16 5, 6, 12 the positive and negative signal inputs to, and the output from, the input gain adjusting signal amplifier. refer to the graph in figure 4 for guidance on setting level sensitivities to national specifications, and the selection of gain adjusting components.
3 application inf application inf application inf application inf application inf ormation ormation ormation ormation ormation external components external components external components external components external components fig.2 recommended external components - differential input mode + - tip (a) ring (b) input amp v bias v ss + - input amp v bias v ss fig.3 example input configurations differential input common mode input v dd v dd v ss c 1 c 2 c 4 c 3 r 4 r 3 r 2 r 1 v ss v bias v ss 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 FX631dw for use with a clock pulse input - remove xtal (x 1 ) - connect pin 1 to v dd - remove link (pins 3/4) - input clock pulses to clock in tone follower output packet mode output system clock in clock in xtal/clock signal in (+) signal in (-) amp out x 1 xtal/clock clock out xtal component component component component component value value value value value r 1 r feedback r 2 r in (-) r 3 r in (+) r 4 r bias c 1 1.0f 20% c 2 1.0f 20% c 3 c in (-) c 4 c in (+) x 1 3.579545mhz external components external components external components external components external components 1. the values of the input amp gain components illustrated are calculated using the input gain calculation graphs (figures 4 and 5). whilst calculating input gain components, for correct operation, it is recommended that the values of resistors r 1 and r 4 are always greater than, or equal to, 33k w . 2. refer to following pages for advice on microcircuit protection from high and spurious line voltages.
4 application inf application inf application inf application inf application inf ormation ...... ormation ...... ormation ...... ormation ...... ormation ...... v dd =3.3(+/-0.1)volts temp= -40 o cto+85 o c amplifier gain (db) signal level (db) 0db ref: 775mvrms -50 -45 -40 -35 -30 -25 -20 -15 -10 -25 -20 -15 -10 -5 0 5 10 15 20 25 must decode level must not decode level minimum amplifier gain maximum amplifier gain fig.4 input gain calculation graph for v dd = 3.3v fig.5 input gain calculation graph for v dd = 5.0v o o
5 input gain calculation input gain calculation input gain calculation input gain calculation input gain calculation the input amplifier, with its external circuitry, is provided on-chip to set the sensitivity of the FX631 to conform to the user's national level specification with regard to must and must-not decode signal levels. with reference to the graphs in figures 4 and 5, the following steps will assist in the determination of the required gain/attenuation. step 1 step 1 step 1 step 1 step 1 draw two horizontal lines from the y-axis (signal levels (db)). the upper line will represent the required must decode level. the lower line will represent the required must- not decode level. step 2 step 2 step 2 step 2 step 2 mark the intersection of the upper horizontal line and the upper sloping line; drop a vertical line from this point to the x-axis (amplifier gain (db)). the point where the vertical line meets the x-axis will indicate the minimum input amp gain required for reliable decoding of valid signals. step 3 step 3 step 3 step 3 step 3 mark the intersection of the lower horizontal line and the lower sloping line; drop a vertical line from this point to the x-axis. the point where the vertical line meets the x-axis will indicate the maximum allowable input amp gain. input signals at or below the must-not decode level will not be detected as long as the amplifier gain is no higher than this level. select the gain components as described opposite. application inf application inf application inf application inf application inf ormation ...... ormation ...... ormation ...... ormation ...... ormation ...... input gain components input gain components input gain components input gain components input gain components with reference to the gain components shown in figures 2 and 3. the user should calculate and select external components (r 1 , r 2 /c 3 , r 3 /c 4 , r 4 ) to provide an amplifier gain within the limits obtained in steps 2 and 3. component tolerances should not move the gain-figure outside these limits. it is recommended that the designed gain is near the centre of the calculated range. the graphs in figures 4 and 5 are for the calculation of input gain components for an FX631 using a v dd of 3.3 (0.1) or 5.0 (0.5) volts respectively. use this area to keep a permanent record of your calculated gains and components implementation notes implementation notes implementation notes implementation notes implementation notes aliasing aliasing aliasing aliasing aliasing due to the switched-capacitor filters employed in the FX631, care should be taken, with the chosen external components, to avoid the effects of alias distortion. possible alias frequencies: 12khz mode = 52khz 16khz mode = 69khz if these alias frequencies are liable to cause problems and/or interference, it is recommended that anti-alias capacitors are employed across input resistors r 1 and r 4 . values of anti-alias capacitors should be chosen so as to provide a highpass cutoff frequency, in conjunction with r 1 (r 4 ) of approximately 20khz to 25khz (12khz system) or 25khz to 30khz (16khz system). i.e. c = 1 2 x p x f 0 x r 1 when anti-alias capacitors are used, allowance must be made for reduced gain at the spm frequency (12khz or 16khz). microcircuit protection microcircuit protection microcircuit protection microcircuit protection microcircuit protection telephone systems may have high d.c. and a.c. voltages present on the line. if the FX631 is part of a host equipment that has its own signal input protection circuitry, there will be no need for further protection as long as the voltage on any pin is limited to within v dd + 0.3v and v ss -0.3v. if the host system does not have input protection, or there are signals present outside the device's specified limits, the FX631 will require protection diodes at its signal inputs (+ and -). the breakdown voltage of capacitors and the peak inverse voltage of the diodes must be sufficient to withstand the sum of the d.c. voltages plus all expected signal peaks. clock out clock out clock out clock out clock out the clock out pin is intended to drive the FX631 clock in pin only. it is not recommended that it be used to clock other devices within the host equipment.
6 specification specification specification specification specification absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not implied. supply voltage -0.3 to 7.0v input voltage at any pin (ref v ss = 0v) -0.3 to (v dd + 0.3v) sink/source current (supply pins) +/- 30ma (other pins) +/- 20ma total device dissipation (dw/p) @ t amb 25c 800mw max. (d5) @ t amb 25c 550mw max. derating (dw/p) 10mw/c (d5) 9mw/c operating temperature (t op ) : FX631dw/d5/p FX631dw/d5/p FX631dw/d5/p FX631dw/d5/p FX631dw/d5/p -40c to +85c storage temperature range (t st ) : FX631dw/d5/p FX631dw/d5/p FX631dw/d5/p FX631dw/d5/p FX631dw/d5/p -40c to +85c functional limits ...... functional limits ...... functional limits ...... functional limits ...... functional limits ...... min. min. min. min. min. max. max. max. max. max. unit unit unit unit unit supply voltage (v dd ) 3.0 5.5 v at 25c all device characteristics are measured under the following conditions unless otherwise specified: v dd = 3.3v to 5.0v t op = -40 to +85 c. audio level 0db ref: = 775mvrms. noise bandwidth = 50khz. xtal/clock or clock in frequency = 3.579545mhz. 12khz or 16khz system setting. characteristics characteristics characteristics characteristics characteristics see note see note see note see note see note min. min. min. min. min. typ. typ. typ. typ. typ. max. max. max. max. max. unit unit unit unit unit supply current 1 - - 1.1 ma 2 - - 2.2 ma input logic 1 (high) 70 - - %v dd input logic 0 (low) - - 30 %v dd output logic 1 (high) 90 - - %v dd output logic 0 (low) - - 10 %v dd xtal/clock or clock in frequency 3.558918 C 3.589368 mhz high external clock pulse width 100 - - ns low external clock pulse width 100 - - ns input amp d.c. gain 60.0 - - db bandwidth (-3db) - 100 - hz input impedance - 1.0 - m w logic impedances input (system) 0.7 - 3.8 m w (clock in) 10.0 - - m w output - 14.0 30.0 k w overall performance 12khz detect bandwidth 3 11.820 12.180 khz 12khz not-detect frequencies (below 12khz) 3 - - 11.520 khz 12khz not-detect frequencies (above 12khz) 3 12.480 - - khz 16khz detect bandwidth 3 15.760 16.240 khz 16khz not-detect frequencies (below 16khz) 3 - - 15.360 khz 16khz not-detect frequencies (above 16khz) 3 16.640 - - khz sensitivity 1, 4 7.8 10.0 15.5 mvp-p tone operation characteristics signal-to-noise requirements (amp input) 5, 6, 7, 8 22.0 20.0 - db signal-to-voice requirements (amp input) 5, 6, 7, 9 -36.0 -40.0 - db signal-to-voice requirements (amp output) 7, 8 -25.0 - -29.0 db tone follower output response and de-response times 3, 10 - - 10.0 ms packet mode output response and de-response times 3, 10 40.0 - 48.0 ms notes .. .. .. .. .. notes .. .. .. .. .. notes .. .. .. .. .. notes .. .. .. .. .. notes .. .. .. .. ..
7 specification ...... specification ...... specification ...... specification ...... specification ...... notes notes notes notes notes 1. v dd = 3.3v 2. v dd = 5.0v 3. with adherence to signal-to-voice and signal-to noise specifications. 4. with input amp gain setting: 15.5db min /18.0db max . 5. common mode spm and balanced voice signal. 6. immune to false responses. 7. immune to false de-responses 8. with spm and voice signal amplitudes balanced; to avoid false de-responses due to saturation, the peak-to-peak voice+noise level at the output of the input amp (12/16khz filter input) should be no greater than the dynamic range of the device. 9. maximum voice frequencies = 3.4khz 10. response, de-response and power-up response timing. signal input tone notone response delay deresponse delay signal input ...... tone follower output packet mode output ...... tone follower output ...... packet mode output fig.7 examples of input and output relationships system timing system timing system timing system timing system timing 12.00khz 11.82khz 11.52khz f 0 -4% f 0 +4% f 0 -1.5% f 0 +1.5% f 0 12.18khz 12.48khz will-decode frequencies will-not decode frequencies will-not decode frequencies 16.00khz 15.76khz 15.36khz f 0 -4% f 0 +4% f 0 -1.5% f 0 +1.5% f 0 16.24khz 16.64khz will-decode frequencies will-not decode frequencies will-not decode frequencies fig.6 will/will-not decode frequencies application inf application inf application inf application inf application inf ormation ...... ormation ...... ormation ...... ormation ...... ormation ......
8 handling precautions the FX631 is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. package outlines the FX631 is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of this document. pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. not to scale max. body length 10.49mm max. body width 7.59mm not to scale max. body length 20.57mm max. body width 6.60mm not to scale max. body length 8.33mm max. body width 5.38mm FX631dw FX631dw FX631dw FX631dw FX631dw 16-pin plastic s.o.i.c. (d4) (d4) (d4) (d4) (d4) FX631d5 FX631d5 FX631d5 FX631d5 FX631d5 24-pin plastic s.s.o.p. FX631p FX631p FX631p FX631p FX631p 16-pin plastic dil (p3) (p3) (p3) (p3) (p3) or or or or or dering inf dering inf dering inf dering inf dering inf ormation ormation ormation ormation ormation FX631dw FX631dw FX631dw FX631dw FX631dw 16-pin plastic s.o.i.c. (d4) (d4) (d4) (d4) (d4) FX631d5 FX631d5 FX631d5 FX631d5 FX631d5 24-pin plastic s.s.o.p. FX631p FX631p FX631p FX631p FX631p 16-pin plastic dil (p3) (p3) (p3) (p3) (p3)
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